A 128‐channel discrete cosine transform‐based neural signal processor for implantable neural recording microsystems
International Journal of Circuit Theory and Applications2013Vol. 43(4), pp. 489–501
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Abstract
Abstract A 128‐channel neural signal processor for implantable neural recording microsystems is presented. The processor compresses the neural information of 128 simultaneous recording channels using discrete cosine transform, achieving a compression factor of 69 at the expense of a 5.6% root mean square error. The proposed processor is implemented on register transfer level and synthesized in a 65‐nm complementary metal‐oxide semiconductor process. The post‐layout simulated power consumption at 1.2 V is 33.06 μ W (258 nW per channel) at an area cost of 0.46 mm 2 . Copyright © 2013 John Wiley & Sons, Ltd.
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