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Low latency flexible FPGA implementation of point multiplication on elliptic curves over GF(p)

International Journal of Circuit Theory and Applications2016Vol. 45(2), pp. 214–228

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Abstract

Summary Elliptic curve cryptography (ECC) is a branch of Public‐Key cryptography that is widely accepted for secure data exchange in many resource‐limited devices. This paper presents a novel hardware cryptographic processor for ECC over general prime field G F ( p ). It is optimized on circuit level by introducing new parallel modular multiplication algorithm with its efficient hardware architecture, which offers significant improvement over the previously used techniques. Subsequently, on the system level, it is optimized by exploiting available high degree of parallelism using projective coordinates by incorporating four parallel multiplier units. The proposed hardware is implemented on Xilinx Virtex‐4 and Virtex‐6 field programmable gate arrays. A 256‐bit scalar multiplication is completed in 1.43 m s and 2.96 m s in a cycle count of 207 1K on Virtex‐6 and Virtex‐4 field programmable gate array paltforms, respectively. The Virtex‐6 implementation attains a maximum frequency of 144 MHz, occupies 32 4K look‐up‐tables, whereas on Virtex‐4 it is about 70 MHz with 35 7K slices. The results show that the proposed design offers a significant improvement in computation time with a significant reduction in cycle count as compared with the other reported designs. Therefore, it is a good choice to be used in many ECC‐based schemes. Copyright © 2016 John Wiley & Sons, Ltd.

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