An Adaptive Pipelined CORDIC Approach for Izhikevich Neurons and STDP Learning

Abstract

ABSTRACT The performance of neuromorphic systems is primarily determined by the interplay between neurons and learning models. Achieving an optimal trade‐off between their computational accuracy and hardware implementation complexity represents a fundamental challenge in pursuing brain‐like neural network designs. This paper introduces a two‐stage pipelined design for spiking neural networks (SNNs) utilizing an adaptive coordinate rotation digital computer (CORDIC) algorithm. Our approach begins with leveraging the adaptive CORDIC method to efficiently approximate square‐term computations in the Izhikevich neuron model, as well as the exponential calculations involved in the spike timing‐dependent plasticity (STDP) algorithm. In addition, a low‐overhead hardware circuit was developed to record the timing of spike firing. FPGA‐based online learning is subsequently implemented on an adaptive CORDIC Izhikevich neuron network. Performance is assessed regarding resource utilization, power efficiency, operational frequency, and computational accuracy, and the results are benchmarked against the latest advancements in the field. This design utilizes 199 look‐up tables (LUTs) and 336 registers per neuron, achieving a remarkably low power consumption of 4.6 mW. It operates at a maximum frequency of 434.7 MHz, with an average computation latency of 74 ns for a single MPI (message passing interface). Additionally, the STDP mechanism attains a peak operating frequency of 287.2 MHz. These results confirm the precision of the adaptive CORDIC‐based SNN, highlighting its superior performance in high‐speed operation, energy efficiency, and minimal area. Owing to these characteristics, the proposed design is particularly well‐suited for resource‐constrained, latency‐sensitive applications such as edge computing, autonomous robotics, and real‐time sensor processing.