HAPE: A high-level area-power estimation framework for FPGA-based accelerators
Microprocessors and Microsystems2018Vol. 63, pp. 11–27
Citations Over TimeTop 11% of 2018 papers
Related Papers
- → Transfer Learning for Design-Space Exploration with High-Level Synthesis(2020)43 cited
- → High-level Synthesis for Low-power Design(2015)26 cited
- → Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE(2019)9 cited
- → HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS(2023)4 cited
- → Improved Delay Estimation Model for Loop based DSP cores(2019)