Open-loop full-digital duty cycle correction circuit

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Abstract

The duty cycle of the clock is corrected to be 50% by an open-loop full-digital duty cycle correction (DCC) circuit. Due to its open-loop and full-digital architecture, the DCC completes its operation in less than five clock cycles and can be turned off during power-down state without any concern about losing its information. The DCC has been implemented in a 0.35 µm CMOS process and the measured accuracy is ±0.8% for ±10% input clock duty error.

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