High-security asynchronous circuit implementation of AES
IEE Proceedings - Computers and Digital Techniques2006Vol. 153(2), pp. 71–71
Citations Over TimeTop 11% of 2006 papers
Abstract
The authors present a novel circuit implementation of the advanced encryption standard using self-timed dual-rail technology. The design reduces leakage of internal information through balanced power consumption, which is achieved by avoidance of glitches and by data-independent switching behaviour. The design utilises a pipeline structure with built-in controllers and novel, highly balanced security latches.
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