Optimizing power using transformations
Citations Over TimeTop 1% of 1995 papers
Abstract
The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives, and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area.>
Related Papers
- → A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller(2021)3 cited
- → CREAM: combined register and module assignment with floorplanning for low power datapath synthesis(2002)8 cited
- → Reducing dynamic power and leakage power for embedded systems(2003)3 cited
- → Power Optimization by Datapath Width Adjustment(2006)1 cited
- → Reducing power consumption on datapath buses(2010)1 cited