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Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder
2006pp. 182–185
Abstract
This paper describes the implementation of a 256-state, rate 14, soft-decision Viterbi decodel: The implementation explores several variables and design considerations of a Viterbi decodel; testing various methods for low power and throughput capability. By designing the Viterbi decoder using three techniques, a progressive active ACS (Add- Compare-Select), prediction matchel; and reduced read traceback, we take the most efJicient techniques and apply them iteratively to the overall design to achieve 12.7 % of dynamic power consumption with 250Mbps of throughput.
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