Area Efficient Approximate Constant-or Adder

Abstract

Power consumption and speed have been well determined with the help of arithmetic module, adder. So the need of high speed, error tolerance and power efficiency nature of few applications have been improved the development of approximate adders. To increase the effectiveness of integrated circuits, utilizing the tradeoff between accuracy and cost of hardware has a great potential. Various approximate adders have been proposed using this technique. By using systematic methodology, optimizing the architecture for approximate adders have been implemented. The adder is called optimized lower part constant-OR adder (LOCA). The adder has been proposed by redesigning its logic circuit.

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