Microarchitecture of HaL's memory management unit
2002pp. 272–280
D. Chang, Douglas Lyon, C. Chen, Lin Peng, Mehran Massoumi, M. Hakimi, Satish Iyengar, Enlai Li, R. Remedios
Abstract
This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.
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