Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique
Citations Over TimeTop 19% of 2006 papers
Abstract
Two modified triple modular redundancy (TMR) structures based on asynchronous circuit technique are proposed in this paper. Double modular redundancy (DMR) structure uses asynchronous C element to output and keep the correct value of two redundant storage cells. Temporal spatial triple modular redundancy structure with DCTREG (TSTMR-D) uses explicit separated master and slave latch structure of de-synchronous pipeline. Three soft error tolerant 8051 cores with DMR, TMR and TSTMR-D respectively are implemented in SMIC 0.35μm process. Fault injection experiments are also included. The experiment results indicate that DMR structure has a relatively low overhead on both area and latency than TMR, while tolerances SEUs in sequential logic. TSTMR-D structures can tolerance soft errors in both sequential logic and combinational logic with reasonable area and latency overhead.
Related Papers
- → Temporal redundancy latch-based architecture for soft error mitigation(2017)7 cited
- Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy.(2006)
- → Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy(2019)1 cited
- → Defect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logic(2020)2 cited
- Redundancy Management in Multi-modular Redundancy Airborne Computer(2007)