Large Scale Cryogenic Integration Approach for Superconducting High-Performance Computing

Citations Over TimeTop 23% of 2017 papers

Abstract

Superconducting single-flux-quantum-based (SFQ) digital integrated circuits (ICs) are a promising candidate for high-speed and ultralow energy dissipation computing systems. Circuits based on several versions of SFQ-type logic, RQL, and AQFP logic have been demonstrated with complexities reaching up to a few tens of thousands of gates. Packaging many superconducting ICs using microbump (15μm or less) technology and performing high throughput, nearly lossless data transfer between various superconducting and/or CMOS chips are highly desirable for a hybrid superconducting computer architecture, but this density has not yet been demonstrated. An efficient way to achieve this goal is to couple the chips through a passive superconductive multichip module (S-MCM) that distributes information between integrated circuits utilizing lossless superconducting transmission lines. Here we show implementation of such a superconducting base using well-defined impedance lines to couple multiple ICs to enable a cryogenic integration approach for possible future hybrid superconducting computing systems. The use of indium-based microbumps to form interconnects between an S-MCM and superconducting ICs, and its electrical performance, are discussed. Optimized microbumps were used to fabricate interconnections on a large S-MCM by using thermocompression(TC) bonding. From 17200 to 68800 microbumps fabricated in a 5 mm × 5 mm active area of an S-MCM, having pitches ranging from 35 μm to 15 μm, were bonded with a superconducting IC to create a daisy chain structure. In addition, a large active area (10 mm × 10 mm) flip-chip having continuous niobium daisy chains with up to 77,500 bumps with 15 μm bump diameter and 35 μm pitch was also demonstrated. As a case study, an optimized microbump interconnect construction for attaching 16 superconducting chips with a large 32 mm × 32 mm superconducting base was fabricated and tested at room temperature and 4.2 K to study the structural and electrical integrity. Josephson junctions and niobium lines on integrated superconducting chips and the superconducting base maintained their I-V characteristics, which allows the design of building blocks for a superconducting computing system.

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