Power Analysis of HLS-Designed Customized Instruction Set Architectures

Citations Over Time

Abstract

Performance and power consumption are key features for evaluating any processor design. In this paper, we present close attention to the impact on power and energy consumption of customized Instruction Set Architecture (ISA) designed by means of High Level Synthesis (HLS) tools. We compare these results against a full ISA soft processor, Microblaze. Our customized ISA processors greatly reduce the power consumption and usage of hardware resources by limiting the implemented instructions to those relevant to specific applications, while still allowing to run the target software kernels. The power estimations are based on the results obtained from the latest Xilinx Vivado Design Suite. After testing our approach on two relevant test benches-a linear algebra application and an encryption application-results reveal that our proposed customized ISA processors consume only 0.5x - 0.7x total power and 0.2x - 0.6x dynamic power of the fully implemented soft processor with a reasonable performance impact.

Related Papers

• → An instruction set and microarchitecture for instruction level distributed processing(2002)94 cited
• → Dynamic coalescing for 16-bit instructions(2005)20 cited
• → FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW(2016)5 cited
• → An instruction set and microarchitecture for instruction level distributed processing(2003)8 cited
• → Exploiting horizontal and vertical concurrency via the HPSm microprocessor(1987)1 cited