A first-order superscalar processor model
Citations Over TimeTop 10% of 2004 papers
Abstract
A proposed performance model for superscalar processors consists of: 1) a component that models the relationship between instructions issued per cycle and the size of the instruction window under ideal conditions; and 2) methods for calculating transient performance penalties due to branch mispredictions, instruction cache misses, and data cache misses. Using trace-derived data dependence information, data and instruction cache miss rates, and branch miss-prediction rates as inputs, the model can arrive at performance estimates for a typical superscalar processor that are within 5.8% of detailed simulation on average and within 13% in the worst case. The model also provides insights into the workings of superscalar processors and long-term microarchitecture trends such as pipeline depths and issue widths.
Related Papers
- → Exploring configurations of functional units in an out-of-order superscalar processor(1995)25 cited
- → An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts(2005)9 cited
- → Comprehensive study of the features, execution steps and microarchitecture of the superscalar processors(2013)5 cited
- → A Performance Study of Multi-core Out-of-Order Superscalar Processor Architecture(2012)1 cited
- 멀티코어 비순차 수퍼스칼라 프로세서의 성능 연구(2012)