A 1.2V, 3.5μW, 20MS/s, 8-bit comparator with dynamic-biasing preamplifier

Abstract

A comparator with the use of a dynamic-biasing preamplifier is presented in this paper. The dynamic-biasing technique provides the flexibility to control and minimize the current consumption of the preamplifier, thereby optimizing the power consumption of the comparator. With the dynamic-biasing preamplifier, the comparator can also operate at lower supply voltage compared to that using conventional preamplifier structures. In addition, the autozeroing technique is proposed to be incorporated into the dynamic-biasing scheme to improve the comparator resolution. By using a standard 0.18/spl mu/m CMOS process, simulation results show that the comparator can operate down to 1.2V and achieve 8-bit resolution while only 2.9/spl mu/A current is dissipated at 20MS/S.

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