Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Citations Over TimeTop 10% of 2013 papers

Abstract

In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worst-case duration, the average write energy is significantly reduced by the proposed architecture. We developed a light-weight circuit for fast state change detection and bit-line shutdown and evaluated it using a compact STT-RAM model targeting an implementation in a 16nm technology node. Our analysis indicates that at the required write-error rate the proposed architecture reduces write energy by 87.3%∓99.5% depending on the write direction, and on average achieves 96.5% write energy saving in 16 SPEC CPU 2006 applications compared to conventional design. Compared to the best previously known architecture that exploits stochasticity (verify-on-write), we reduce write energy by approximately 6.5×.

Related Papers

• → GC-ARM: Garbage Collection-Aware RAM Management for Flash Based Solid State Drives(2012)14 cited
• → Integrated write buffer management for solid state drives(2014)5 cited
• RFLRU: A Buffer Cache Management Algorithm for Solid State Drive to Improve the Write Performance on Mixed Workload(2014)
• → MG-Buffer: A Read/Write-Optimized Multi-Grained Buffer Management Scheme for Database Systems(2019)1 cited
• → Considerations for Designing an Integrated Write Buffer Management Scheme for NAND-based Solid State Drives(2013)