Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU
2011pp. 78–80
Citations Over TimeTop 10% of 2011 papers
Tim Fischer, Srikanth Arekapudi, Eric Busta, C. Dietz, Michael Golden, S. Hilker, Atsushi Horiuchi, Kate Hurd, D. Johnson, H. McIntyre, Samuel Naffziger, James Vinh, Jonathan M. White, Karen S. Wilcox
Abstract
AMD's 2-core "Bulldozer" module contains 213 million transistors in an 11 metal layer 32nm HKMG SOI CMOS process and is designed to operate from 0.8 to 1.3V. This new micro-architecture improves performance and frequency while reducing area and power compared to a previous AMD x86-64 CPU in the same process. To achieve these goals, the design reduced the number of F04 inverter delays/cycle by more than 20%, achieving higher frequencies in the same power envelope even with increased core counts. The 2-core CPU module area (including 2MB L2 cache) is 30.9mm 2 . The Bulldozer micro-architecture is cycle-based, using soft-edge flip-flops (SEF) to provide high-frequency performance, process variation tolerance, and low power consumption.