Sequential Prefetch Cache Sizing for Maximal Hit Rate

Citations Over TimeTop 11% of 2010 papers

Abstract

We propose a prefetch cache sizing module for use with any sequential prefetching scheme and evaluate its impact on the hit rate. Disk array caches perform sequential prefetching by loading data contiguous to I/O request data into the array cache. If the I/O workload has sequential locality, then data prefetched in response to sequential accesses in the workload will receive hits. Different schemes prefetch different data, so the prefetch cache size requirement varies. Moreover, the proportion of sequential and random requests in the workload and their interleaving pattern affects the size requirement. If the cache is too small, then prefetched data would get evicted from the cache before a request for the data arrives, thus lowering the hit rate. If the cache is too large, then valuable cache space is wasted. We present a simple sizing module that can be added to any prefetching scheme to ensure that the prefetch cache size is adequately matched to the requirement of the prefetching scheme on a dynamic workload comprising multiple streams. We analytically compute the maximal hit rate achievable by popular prefetching schemes and through simulations, show that our sizing module maintains the prefetch cache at a size that nearly achieves this maximal hit rate.

Related Papers

• → Location cache(2004)28 cited
• → ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems(2009)5 cited
• → The i486 microprocessor integrated cache and bus interface(2002)4 cited
• → Hybrid-way Cache for Mobile Processors(2011)3 cited
• → Composite Pseudo-Associative Cache for Mobile Processors(2010)2 cited