Test Challenges for 3D Integrated Circuits
IEEE Design & Test of Computers2009Vol. 26(5), pp. 26–35
Citations Over TimeTop 1% of 2009 papers
Abstract
One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area. Researchers are investigating various 3D IC manufacturing processes that are particularly relevant to testing and DFT. In terms of the process and the level of assembly that 3D ICs require, we can broadly classify the techniques as monolithic or as die stacking.
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