Advanced synchronisation and decoding in RFID reader receivers

Citations Over TimeTop 10% of 2009 papers

Abstract

This paper focuses on one of the major challenges in RFID reader receivers, namely the data synchronisation and decoding at the RFID reader. According to the most widely used RFID standards, the data rate in RFID tag to reader communications is subject to variations within more than one decade, and may deviate from its nominal frequency up to 22%. This results in strong difficulties in synchronising and decoding this data at the receiver of the RFID reader. In order to achieve synchronisation and decoding, a sophisticated algorithm based on correlations is presented. The algorithm is optimised in terms of resource consumption to be processed on an FPGA or ASIC. Implementation details are presented as well as measurements, showing the performance of the receiver.

Related Papers

• → Structured ASIC, evolution or revolution?(2004)78 cited
• → Architectures for adaptive weight calculation on ASIC and FPGA(2003)42 cited
• → Use of VPR in Design of FPGA Architecture(2006)9 cited
• → Physical design tradeoffs for ASIC technologies(2002)3 cited
• On FPGA Development(1999)