Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing2006Vol. 53(8), pp. 707–711
Citations Over TimeTop 17% of 2006 papers
Abstract
Novel one- and two-dimensional systolic structures are designed for computation of circular convolution using distributed arithmetic (DA). The proposed structures involve significantly less memory and less area-delay complexity compared with the existing DA-based structures for circular convolution. Besides, it is shown that the proposed systolic designs for circular convolution can be used for computation of linear convolution as well
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