An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors

Citations Over TimeTop 10% of 2005 papers

Abstract

Instruction set customization is an effective way to improve processor performance. Critical portions of applicationdata-flow graphs are collapsed for accelerated execution on specialized hardware. Collapsing dataflow subgraphs will compress the latency along critical paths and reduces the number of intermediate results stored in the register file. While custom instructions can be effective, the time and cost of designing a new processor for each application is immense. To overcome this roadblock, this paper proposes a flexible architectural framework to transparently integrate custom instructions into a general-purpose processor. Hardware accelerators are added to the processor to execute the collapsed subgraphs. A simple microarchitectural interface is provided to support a plug-and-play model for integrating a wide range of accelerators into a pre-designed and verified processor core. The accelerators are exploited using an approach of static identification and dynamic realization. The compiler is responsible for identifying profitable subgraphs, while the hardware handles discovery, mapping, and execution of compatible subgraphs. This paper presents the design of a plug-and-play transparent accelerator system and evaluates the cost/performance implications of the design.

Related Papers

• → Platform-based resource binding using a distributed register-file microarchitecture(2006)33 cited
• → Chained In-Order/Out-of-Order DoubleCore Architecture(2006)3 cited
• → Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture(2007)2 cited
• → The microarchitecture of a low power register file(2003)1 cited
• → The microarchitecture of a low power clustered register file for parallel processors(2005)