Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems
Citations Over TimeTop 10% of 2011 papers
Abstract
Multicore architectures, especially chip multi-processors, have been widely acknowledged as a successful design paradigm. Existing approaches primarily target application-driven partitioning of the shared cache to alleviate inter-core cache interference so that both performance and energy efficiency are improved. Dynamic cache reconfiguration is a promising technique in reducing energy consumption of the cache subsystem for uniprocessor systems. In this paper, we present a novel energy optimization technique which employs both dynamic reconfiguration of private caches and partitioning of the shared cache for multicore systems with real-time tasks. Our static profiling based algorithm is designed to judiciously find beneficial cache configurations (of private caches) for each task as well as partition factors (of the shared cache) for each core so that the energy consumption is minimized while task deadline is satisfied. Experimental results using real benchmarks demonstrate that our approach can achieve 29.29% energy saving on average compared to systems employing only cache partitioning.
Related Papers
- → Set Utilization Based Dynamic Shared Cache Partitioning(2011)5 cited
- → Composite Pseudo-Associative Cache for Mobile Processors(2010)2 cited
- → Capturing dynamic memory reference behavior with adaptive cache topology(1998)2 cited
- → Reducing cache conflicts by multi-level cache partitioning and array elements mapping(2002)1 cited
- → WCRT analysis for a uniprocessor with a unified prioritized cache(2005)