Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array

Citations Over TimeTop 10% of 2022 papers

Abstract

Transformer model architectures have recently received great interest in natural language, machine translation, and computer vision, where attention mechanisms are their building blocks. However, the attention mechanism is expensive because of its intensive matrix computations and complicated data flow. The existing hardware architecture has some disadvantages for the computing structure of attention, such as inflexibility and low efficiency. Most of the existing papers accelerate attention by reducing the amount of computation through various pruning algorithms, which will affect the results to a certain extent with different sparsity. This paper proposes the hardware accelerator for the multi-head attention (MHA) on field-programmable gate arrays (FPGAs) with reconfigurable architecture, efficient systolic array, and hardware-friendly radix-2 softmax. We propose a novel method called Four inputs Processing Element (FPE) to double the computation rate of the data-aware systolic array (SA) and make it efficient and load balance. Especially, the computation framework is well designed to ensure the utilization of SA efficiently. Our design is evaluated on a Xilinx Alveo U250 card, and the proposed architecture achieves 51.3×, 17.3× improvement in latency, and 54.4×, 17.9× energy savings compared to CPU and GPU.

Related Papers

• → A Multimedia Tool for Teaching Reconfigurable Computing(2009)5 cited
• → Optimizing Resources of an FPGA-based Smart Camera Architecture(2007)4 cited
• → Scalar quantisation using a fast systolic array(1997)5 cited
• Realization of BP Algorithm in FPGA Based on Systolic Array Architecture(2006)
• → PRMC: a multicontext FPGA with partially reconfigurable logic planes(2004)