Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability

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Abstract

Rapid progress in CMOS technology since the late 1990s has increased the vulnerability of processors toward faults. Subsequently, the focus of computer architects has shifted toward designing fault-tolerance methods for processor architectures. Concurrently, chip designers have encountered high-order challenges for designing fault-tolerant processor architectures. For processor cores, redundancy-based fault-tolerance methods for fault detection at the core, micro-architectural, thread, and software levels are discussed. Similar applicable redundancy-based fault-tolerance methods for cache memory and hardware accelerators are also presented in the article. Recent trends in fault-tolerant quantum computing and quantum error correction are also discussed. The classification of state-of-the-art techniques presented will help researchers organize their work on established lines.

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