Vectorization for SIMD architectures with alignment constraints

Citations Over TimeTop 1% of 2004 papers

Abstract

When vectorizing for SIMD architectures that are commonly employed by today's multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Prior research has focused primarily on vectorizing loops where all memory references are properly aligned. An important aspect of this problem, namely, how to vectorize misaligned memory references, still remains unaddressed.This paper presents a compilation scheme that systematically vectorizes loops in the presence of misaligned memory references. The core of our technique is to automatically reorganize data in registers to satisfy the alignment requirement imposed by the hardware. To reduce the data reorganization overhead, we propose several techniques to minimize the number of data reorganization operations generated. During the code generation, our algorithm also exploits temporal reuse when aligning references that access contiguous memory across loop iterations. Our code generation scheme guarantees to never load the same data associated with a single static access twice. Experimental results indicate near peak speedup factors, e.g., 3.71 for 4 data per vector and 6.06 for 8 data per vector, respectively, for a set of loops where 75% or more of the static memory references are misaligned.

Related Papers

• → Vectorization for SIMD architectures with alignment constraints(2004)42 cited
• → Performance evaluation of implicit and explicit SIMDization(2018)13 cited
• → SIMDization of Small Tensor Multiplication Kernels for Wide SIMD Vector Processors(2018)3 cited
• → PVL: Parallelization and Vectorization of Affine Perfectly Nested-Loops Considering Data Locality on Short-Vector Multicore Processors using Intrinsic Vectorization(2017)3 cited
• Research and Improvement of SIMD Vecotrization Algorithms on Non-multimedia Applications(2009)