MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution
Electronics2021Vol. 10(15), pp. 1816–1816
Citations Over Time
J. Mauricio, Lluís Freixas Coromina, A. Sanuy, S. Gomez Fernandez, R. Manera Escalero, J. Marín, J.M. Pérez, E. Picatoste Olloqui, P. Rato Mendes, David Sánchez, A. Sanmukh, O. Vela, D. Gascón
Abstract
This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.
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