Automatic Generation Strategy for Standard Cell Layout in DTCO Process Based on Reinforcement Learning

Abstract

DTCO (Design–Technology Co-optimization) facilitates communication between the design and process flows, thereby expediting the cycle of the chip development pipeline. Within the DTCO framework, the development of a standard cell library, which entails the rapid generation of standard cell layouts, constitutes a crucial aspect in enhancing the efficiency of digital integrated circuit development. In light of the issue of the substantial time consumption associated with manual layout design prevalent in the industry, a novel method for the automatic generation of standard cell layouts, leveraging reinforcement learning for placement and the Dijkstra algorithm for routing, is proposed. Compared with traditional automatic layout algorithms, the proposed methodology exhibits enhanced adaptability. When accounting for the influence of technological node variations on design alterations, the device information and key design rule parameters are configured as adjustable variables to accommodate the migration across different processes. It is demonstrated that the proposed method can accelerate the DTCO cycle and enable the migration of the standard cell layout from the 55 nm process to the 28 nm process of a specific foundry. It is anticipated that this approach can offer novel perspectives for the advancement of EDA tools dedicated to the automatic generation of standard cell layouts.

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