A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm

Abstract

As the integrated circuit process nodes are continuously reduced, higher complexity and accuracy requirements are imposed on the design rule checking (DRC) of standard cell layouts. Traditional manual repair methods are inefficient and prone to errors. A standard cell layout DRC automatic repair strategy based on an improved simulated annealing algorithm is proposed to address this issue. The proposed method quantifies the degree of graphic conflict by dynamically adjusting the annealing parameters; the high-conflict areas and repair paths are optimized. Meanwhile, the proposed method supports the repair of DRC rules at different process nodes ranging from MOSFET (28 nm) to FinFET (14 nm). Experiments results demonstrate that the proposed method outperforms traditional methods in both repair time and quality. Compared to manual repair, about 70% (MOSFET process) and 80% (FinFET process) of time can be saved by the proposed method, and new violations can be avoided during the repair process. Compared with traditional simulated annealing algorithms, approximately 40% (MOSFET process) and 50% (FinFET process) of the running time can be saved, and 100% elimination rate of DRC violations is achieved. The proposed method provides a fully automated and highly reliable DRC repair solution for integrated circuit layout design.