Jae‐Joon Kim

Publications by Year

Research Areas

Advanced Memory and Neural Computing, Semiconductor materials and devices, Ferroelectric and Negative Capacitance Devices, Low-power high-performance VLSI design, Advancements in Semiconductor Devices and Circuit Design

Most-Cited Works

• → A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS(2009)476 cited
• → A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS(2008)123 cited
• → Negative Transconductance Heterojunction Organic Transistors and their Application to Full‐Swing Ternary Circuits(2019)122 cited
• → Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array(2019)89 cited
• → A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations(2005)88 cited
• → Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning(2019)86 cited
• → Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability(2009)84 cited
• → SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage(2009)76 cited
• → 8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors(2017)74 cited
• → Improved Synapse Device With MLC and Conductance Linearity Using Quantized Conduction for Neuromorphic Systems(2018)72 cited