Shih‐Hung Chen

Publications by Year

Research Areas

Electrostatic Discharge in Electronics, Semiconductor materials and devices, Integrated Circuits and Semiconductor Failure Analysis, Advancements in Semiconductor Devices and Circuit Design, 3D IC and TSV technologies

Most-Cited Works

• → A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts(2012)39 cited
• → Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology(2007)30 cited
• → Overview of 3D NAND Flash and progress of vertical gate (VG) architecture(2012)29 cited
• → Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs(2009)29 cited
• → Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses(2008)29 cited
• → Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology(2021)27 cited
• A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure(2011)
• → A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)(2012)25 cited
• → ESD in FinFET technologies: Past learning and emerging challenges(2013)24 cited
• → Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection(2009)23 cited