Daeyeal Lee
University of California San Diego(US)
Publications by Year
Research Areas
VLSI and FPGA Design Techniques, VLSI and Analog Circuit Testing, Advancements in Semiconductor Devices and Circuit Design, Integrated Circuits and Semiconductor Failure Analysis, Low-power high-performance VLSI design
Most-Cited Works
- → Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT(2021)49 cited
- → A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology(2012)48 cited
- → SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes(2020)41 cited
- → PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes(2021)26 cited
- → Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)(2021)22 cited
- → Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules(2020)16 cited
- → SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm(2020)15 cited
- → A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT(2020)14 cited
- → Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes(2021)13 cited
- → Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis(2022)12 cited