Abhijit Jas
Intel (United States)(US)
Publications by Year
Research Areas
VLSI and Analog Circuit Testing, Radiation Effects in Electronics, Integrated Circuits and Semiconductor Failure Analysis, Low-power high-performance VLSI design, Engineering and Test Systems
Most-Cited Works
- → An efficient test vector compression scheme using selective huffman coding(2003)275 cited
- → Test vector decompression via cyclical scan chains and its application to testing core-based designs(2002)271 cited
- → Scan vector compression/decompression using statistical coding(2003)264 cited
- → Test vector encoding using partial LFSR reseeding(2002)229 cited
- → Virtual scan chains: a means for reducing scan length in cores(2002)93 cited
- → Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme(2002)62 cited
- → Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller(2010)61 cited
- → Weighted pseudorandom hybrid BIST(2004)57 cited
- → Using an embedded processor for efficient deterministic testing of systems-on-a-chip(2003)53 cited
- → Achieving high encoding efficiency with partial dynamic LFSR reseeding(2004)31 cited