Ranjani Narayan
Morpho (United States)(US)
Publications by Year
Research Areas
Parallel Computing and Optimization Techniques, Interconnection Networks and Systems, Embedded Systems Design Techniques, Numerical Methods and Algorithms, Low-power high-performance VLSI design
Most-Cited Works
- → REDEFINE(2009)58 cited
- → Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat(2015)29 cited
- → Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures(2009)20 cited
- → A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths(2014)17 cited
- → High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit(2013)15 cited
- → Compiling HPC Kernels for the REDEFINE CGRA(2015)15 cited
- → RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router(2008)14 cited
- → Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations(2015)14 cited
- → Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR)(2014)13 cited
- → Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs(2014)13 cited