Shianling Wu
Kyushu Institute of Technology(JP)Syntek Technologies (United States)(US)
Publications by Year
Research Areas
VLSI and Analog Circuit Testing, Integrated Circuits and Semiconductor Failure Analysis, Engineering and Test Systems, Low-power high-performance VLSI design, VLSI and FPGA Design Techniques
Most-Cited Works
- → VirtualScan: a new compressed scan technology for test cost reduction(2005)105 cited
- A Sequential Circuit Test Generation System.(1985)
- → Built-in Self-Test for Digital Integrated Circuits(1994)59 cited
- → VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG(2008)39 cited
- → At-speed logic BIST architecture for multi-clock designs(2006)24 cited
- → A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing(2006)22 cited
- → Ultrascan: using time-division demultiplexing/multiplexing (TDDM/TDM) with virtualscan for test cost reduction(2006)21 cited
- → Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains(2010)15 cited
- → A non-enumerative path delay fault simulator for sequential circuits(2002)13 cited
- → Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains(2010)12 cited