Wafer-Scale Synthesis of High-Quality Semiconducting Two-Dimensional Layered InSe with Broadband Photoresponse

Citations Over TimeTop 1% of 2017 papers

Abstract

Large-scale synthesis of two-dimensional (2D) materials is one of the significant issues for fabricating layered materials into practical devices. As one of the typical III-VI semiconductors, InSe has attracted much attention due to its outstanding electrical transport property, attractive quantum physics characteristics, and dramatic photoresponse when it is reduced to atomic scale. However, scalable synthesis of single phase 2D InSe has not yet been achieved so far, greatly hindering further fundamental studies and device applications. Here, we demonstrate the direct growth of wafer-scale layered InSe nanosheets by pulsed laser deposition (PLD). The obtained InSe layers exhibit good uniformity, high crystallinity with macro texture feature, and stoichiometric growth by in situ precise control. The characterization of optical properties indicates that PLD grown InSe nanosheets have a wide range tunable band gap (1.26-2.20 eV) among the large-scale 2D crystals. The device demonstration of field-effect transistor shows the n-type channel feature with high mobility of 10 cm2 V-1 s-1. Upon illumination, InSe-based phototransistors show a broad photoresponse to the wavelengths from ultraviolet to near-infrared. The maximum photoresponsivity attains 27 A/W, plus a response time of 0.5 s for the rise and 1.7 s for the decay, demonstrating the strong and fast photodetection ability. Our findings suggest that the PLD grown InSe would be a promising choice for future device applications in the 2D limit.

Related Papers

• → Wafer-On-Wafer-On-Wafer (WoWoW) Integration Having Large-scale High Reliability Fine 1 μm Pitch Face-To-Back (F2B) Cu-Cu Connections and Fine 6 μm Pitch TSVs(2024)9 cited
• → Self-assembly technology for reconfigured wafer-to-wafer 3D integration(2010)24 cited
• → Process Induced Wafer Warpage Optimization for Multi-chip Integration on Wafer Level Molded Wafer(2019)4 cited
• → Mechanical Reliability of Silicon Wafers with Through-Wafer Vias for Wafer-Level Packaging(2002)8 cited
• On the Scale and Quality Idea of Civilian-run Universities(2002)