A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme
IEEE Journal of Solid-State Circuits2000Vol. 35(11), pp. 1648–1654
Citations Over TimeTop 10% of 2000 papers
S. Atsumi, Akira Umezawa, Tôru Tanzawa, T. Taura, H. Shiga, Yoshimichi Takano, T. Miyaba, M. Matsui, Hiroshi Watanabe, K. Isobe, S. Kitamura, Shigeru Yamada, M. Saito, Seiichi Mori, T. Watanabe
Abstract
A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.
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