Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging

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Abstract

Fan-out wafer level packaging (FO-WLP) technology has lots of advantages of small form factor, higher I/O density, cost effective and high performance. However, wafer warpage is one big challenge during wafer process, which needs to be addressed for successful process integration. In this study, methodology to understand and reduce wafer warpage at different processes is presented in terms of geometry design, material selection, and process optimization through finite element analysis (FEA), theoretical calculation and experimental data. Quick wafer warpage evaluation method is proposed and compared with FEA results for the molded wafer. Wafer process dependent modeling is established and results are validated by experimental data for both mold-first and RDL-first methods. Key parameters are identified based on FEA modeling results: thickness ratio of die to total mold thickness, compression molding condition, molding compound and support wafer materials, dielectric material and Cu RDL design.

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