An efficient numerical model of CMOS latch-up

Abstract

A one-dimensional numerical model of latch-up in bulk CMOS structures is presented. The model simulates the triggering and sustaining regimes of the parasitic SCR, yielding results nearly equivalent to those obtained using two-dimensional analysis, but with two orders of magnitude-lower computational cost. The model is used to obtain the SCR switching characteristics of typical CMOS based on two-dimensional impurity cross sections, and parameter sensitivities are examined.

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