Scalable HMM based inference engine in large vocabulary continuous speech recognition

Citations Over TimeTop 11% of 2009 papers

Abstract

Parallel scalability allows an application to efficiently utilize an increasing number of processing elements. In this paper we explore a design space for application scalability for an inference engine in large vocabulary continuous speech recognition (LVCSR). Our implementation of the inference engine involves a parallel graph traversal through an irregular graph-based knowledge network with millions of states and arcs. The challenge is not only to define a software architecture that exposes sufficient fine-grained application concurrency, but also to efficiently synchronize between an increasing number of concurrent tasks and to effectively utilize the parallelism opportunities in today's highly parallel processors. We propose four application-level implementation alternatives we call ldquoalgorithm stylesrdquo, and construct highly optimized implementations on two parallel platforms: an Intel Core i7 multicore processor and a NVIDIA GTX280 manycore processor. The highest performing algorithm style varies with the implementation platform. On 44 minutes of speech data set, we demonstrate substantial speedups of 3.4times on Core i7 and 10.5times on GTX280 compared to a highly optimized sequential implementation on Core i7 without sacrificing accuracy. The parallel implementations contain less than 2.5% sequential overhead, promising scalability and significant potential for further speedup on future platforms.

Related Papers

• → A framework for automatic custom instruction identification on multi-issue ASIPs(2014)3 cited
• → Peeling algorithm for custom instruction identification(2010)3 cited
• → Optimizing Speedup on Multicore Platform with OpenMP Schedule Clause and Chunk Size(2020)2 cited
• Tunable Instruction Set Extension Identification(2011)
• → ISA customization for application specific instruction set processors(2015)