A framework for automatic custom instruction identification on multi-issue ASIPs

Citations Over TimeTop 25% of 2014 papers

Abstract

Custom Instruction Identification is an important part in the design of efficient Application-Specific Processors (ASIPs). It consists of profiling of a given application to find patterns of basic operations that are frequently executed. Operations of such patterns can be implemented together as a single custom instruction to speedup the execution of the application. Because of the problem's high complexity, several methods have been proposed for specific single-issue (RISC) processors and architectures, limiting the shape and size of custom instructions that can actually be identified and, possibly, implemented. In this paper, we propose and discuss an efficient custom instruction set identification method and corresponding automatic tool for multi-issue VLIW ASIPs, which search for the common operation patterns of the most frequently executed basic blocks of a given application, with different sizes and shapes. The speedup results for the custom instructions identified by our tool are provided for a set of benchmark applications. The speedup is up to 68%, with only a few custom instructions used.

Related Papers

• → A framework for automatic custom instruction identification on multi-issue ASIPs(2014)3 cited
• → IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements(2002)14 cited
• → HiPAR-DSP: a parallel VLIW RISC processor for real time image processing applications(2002)9 cited
• → High-performance instruction-set simulator for TMS320C62x DSP(2010)1 cited
• → Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors(1996)20 cited