FPGA Implementation of SRAM-based Ternary Content Addressable Memory

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Abstract

Content Addressable Memory (CAM) is a special memory that accomplishes search operation in a single clock cycle but CAM has disadvantages like low bit density and high cost per bit. In this paper, we present an implementation of a 512 x 36 SRAM-based TCAM (SR-TCAM) on a Virtex-5 FPGA, which is the strength of SR-TCAM because currently classical TCAMs cannot be implemented on FPGA. We have used two synthesis optimizations (BRAM-AUTO and BRAM = BLOCK_POWER2) using BRAMs on FPGA. Thus, user can choose design parameters that are suitable for his application. The power data has been measured using Xilinx X-Power by using activities for search operations of SR-TCAM. We have computed power consumption by taking the average of 1000 search operations with 100 MHz clock speed to have better power estimation, which results, for one of the design, in an average power consumption of 2.11 mW. SR-TCAM exploits dense SRAM and achieves comparable search performance in two clock cycles. Thus, SR-TCAM is a feasible and practical alternative to traditional CAMs.

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