Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

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Abstract

PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, turned-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

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