65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate V_th Monitoring and Body Bias for NMOS and PMOS

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Abstract

We design a technique to separately measure the Vth of NMOS and PMOS. This technique is used to determine the body bias of NMOS and PMOS individually. Prototype chips with 1Mb 0.51 mm2 high-density SRAM cells using a 65 nm low-power process are fabricated and achieve 1.0 V operation, even when considering actual Vth variation.

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