Masanao Yamaoka

Publications by Year

Research Areas

Low-power high-performance VLSI design, Quantum Computing Algorithms and Architecture, Advancements in Semiconductor Devices and Circuit Design, Semiconductor materials and devices, VLSI and FPGA Design Techniques

Most-Cited Works

• → A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing(2015)362 cited
• → Silicon on thin BOX: a new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control(2005)143 cited
• → Low-power embedded SRAM modules with expanded margins for writing(2005)135 cited
• → 24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing(2015)111 cited
• → STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions(2020)110 cited
• → A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor(2005)99 cited
• → Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology(2004)98 cited
• → 90-nm Process-Variation Adaptive Embedded SRAM Modules With Power-Line-Floating Write Technique(2006)94 cited
• → Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM(2008)90 cited