Architecting energy efficient crossbar-based memristive random-access memories
2015pp. 1–6
Citations Over TimeTop 10% of 2015 papers
Abstract
Memristive devices are promising candidates for future high-density, power-efficient memories. The sneak path problem of purely-resistive crossbars and the inherent nanowire voltage drop, however, prevent the use of memristors in large-scale memory systems. In this paper we provide a simple yet flexible 3D memory organization and decoding scheme for memristive crossbars that exploits the benefits of the CMOL interface and avoid the limitations of conventional resistive crossbars. We propose an electrical model of the system to simulate and estimate its delay and energy consumption and show that such memories provide high read/write concurrency with power consumption per read/write operation that is significantly lower than that of DRAM.
Related Papers
- → Analysis of a memristor based 1T1M crossbar architecture(2011)21 cited
- → Tolerance to defective memristors in a neuromorphic learning circuit(2014)13 cited
- → Implementation of organic RRAM with ink-jet printer: from design to using in RFID-based application(2021)
- → Optimizing the Distribution of Memristance Values of Memristive Synapses for Reducing Power Consumption in Analog Memristor Crossbar Based Neural Networks(2019)