Daniele Gardellini

Publications by Year

Research Areas

Radio Frequency Integrated Circuit Design, Advancements in PLL and VCO Technologies, Semiconductor materials and devices, VLSI and Analog Circuit Testing, Optical Network Technologies

Most-Cited Works

• → A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology(2012)174 cited
• → A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS(2012)68 cited
• → A 28Gb/s source-series terminated TX in 32nm CMOS SOI(2012)38 cited
• → A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology(2014)25 cited
• → A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology(2012)25 cited
• → A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology(2013)9 cited
• A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS(2011)
• → A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS(2017)1 cited