Santiago Remersaro
Mentor Technologies(US)
Publications by Year
Research Areas
VLSI and Analog Circuit Testing, Integrated Circuits and Semiconductor Failure Analysis, Advancements in Photolithography Techniques, VLSI and FPGA Design Techniques, Engineering and Test Systems
Most-Cited Works
- → Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs(2006)236 cited
- → Low Shift and Capture Power Scan Tests(2007)53 cited
- → ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction(2008)26 cited
- → Scan-Based Tests with Low Switching Activity(2007)22 cited
- → A scalable method for the generation of small test sets(2009)12 cited
- → On low power test and DFT techniques for test set compaction(2008)3 cited
- → Analysis and improvements to MATE algorithm(2005)2 cited
- → ADAPTIVE ALGORITHMS AND EXPERIMENTAL RESULTS OF A BOLUS CHASING CT SCANNER(2005)1 cited
- Preferred Fill: A Scalable MethodtoReduceCapture PowerforScan BasedDesigns(2006)