D. Storaska

Publications by Year

Research Areas

Radio Frequency Integrated Circuit Design, Semiconductor materials and devices, Advancements in PLL and VCO Technologies, Electromagnetic Compatibility and Noise Suppression, VLSI and Analog Circuit Testing

Most-Cited Works

• → A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology(2012)174 cited
• → A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology(2014)25 cited
• → A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology(2012)25 cited
• → 10+ gb/s 90-nm CMOS serial link demo in CBGA package(2005)19 cited
• → A 2.9ns random access cycle embedded DRAM with a destructive-read(2003)15 cited
• → A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture(2002)10 cited
• → A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology(2013)9 cited
• → 10+ Gb/s 90nm CMOS serial link demo in CBGA package(2004)6 cited
• → A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs(2000)5 cited
• Vertically-Folded Bitline Architecture(2001)