A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
2007pp. 436–591
Citations Over TimeTop 1% of 2007 papers
Mike Harwood, N. Warke, R. S. Simpson, Tom Leslie, A. Amerasekera, Sean Batty, D. Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, P.C. Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, A. J. Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth
Abstract
A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of -15 is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm 2 per TX/RX pair
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